The International Technology Roadmap for Semiconductors (ITRS) identifies the technology push towards hybridization of synchronous and asynchronous timing conventions and a possible shift to asynchronous or GALS (globally-asynchronous locally-synchronous) design techniques. The winter school will address these issues.
The school presumes that attendees will have a background in synchronous (clocked) circuit design, but not in asynchronous circuit design. Consequently, the school starts by introducing robust asynchronous design principles, before moving on to mixed synchronous/asynchronous design issues.
The programme is available as a PDF download flyer and there is a PowerPoint side advert.
| Monday 3 January 2005 | Arrival and evening reception |
| No talks on this day | |
| Please check into your accommodation (most people are at Gonville and Caius College) | |
| The reception is from 6pm - further details below. | |
| Tuesday 4 January 2005 | Introduction to asynchronous circuits |
| Jens Sparsų et al. will present material from chapters 1 to 8 of Principles of asynchronous circuit design - a systems perspective by Sparsų and Furber | |
| Wednesday 5 January 2005 | Synthesis of asynchronous controllers and interfaces |
| Morning: Alex Yakovlev et al. will introduce the use of signal transition graphs (STGs) and Petri nets to synthesise asynchronous circuits | |
| Afternoon: Hands-on session - designing asynchronous controllers using Petrify | |
| Thursday 6 January 2005 | Mixing synchronous and asynchronous techniques |
| Morning: Luciano Lavagno et al. - Transforming synchronous circuits into asynchronous circuits using the desynchronization technique | |
| Afternoon part 1: David Kinniment - Synchronisers and arbitration | |
| Afternoon part 2: Simon Moore - Globally Asynchronous Locally Synchronous (GALS) systems design | |
| Friday 7 January 2005 | Research topics and hands-on session |
| Morning: Research topics in mixed synchronous/asynchronous design | |
| Afternoon: Doug Edwards et al. - an introduction to the Balsa asynchronous circuit synthesis system plus an introduction to the use of the new simulation and visualisation tools to debug and optimise Balsa asynchronous circuits. This will be a hands-on session. | |
Timing: we will aim to run the Tuesday to Friday sessions around the
following format:
| 09:30 | First lecture | |
| 10:30 | break | |
| 11:30 | Second lecture | |
| 12:30 | Lunch | |
| 14:00 | Third lecture | |
| 15:30 | break | |
| 16:00 | Fourth lecture | |
| 17:30 | Finish lecture | |
| 19:00 | Dinner |
The reception on the Monday evening will be at the Slug and Lettuce Pub (near Gonville and Caius college) from 6pm. The idea is to informally meet up with people over a beer and have food as required.
Dinner will be provided at Gonville and Caius College on Tue and Thur evenings. Dinner will be at Trinity Hall on the Wed.
Registration is now closed.
| Registration Fee | ||
| Academic/student rate | £200 | (€300) |
| Industrial rate | £500 | (€750) |
This fee includes a copy of the proceedings, reception on Monday, lunches for Tuesday to Friday and dinners on Tuesday, Wednesday and Thursday. Accommodation is in addition.
Student room accommodation at Gonville and Caius College will be available for £140 for 5 nights (arrive Monday and depart Saturday) which can be booked with the registration.
A deligates list is now available. Please ensure your friends are registered.
This winter school is being hosted by the Computer Laboratory, University of Cambridge. Directions to the Computer Laboratory building.
Accommodation will be at Gonville and Caius College, one of the 35 Cambridge Colleges
Cambridge has little parking for cars, and what there is is expensive. We can provide some overnight parking at the Computer Lab by prior arrangement. However, we advise that you travel by train or coach. The train station is 1 mile from the centre and there is a shuttle bus which runs every 8 minutes into the centre. The coach station (Drummer Street) is right in the centre. The Computer Lab is approximately 1 mile from the centre.
Links:
The Working Group on Asynchronous Circuit Design (ACiD-WG) is organising this event at the end of a period of funding from the European Commission. Previous well-attended schools have been held in Grenoble, France in 2002 and Lyngby, Denmark in 1997. The working group has also run many workshops and other events - see the ACiD-WG home page for details.
| Local organiser: | Simon Moore | (winter-school@cl.cam.ac.uk) | |
| Secretarial Support: | Kate Ellis | (winter-school@cl.cam.ac.uk) | tel: +44 (0)1223 763500 |
| ACiD-WG Coordinator: | Mark Josephs |